1. Field of the Invention
The present invention relates to the reading from memory circuits, and in particular to sense amplifiers.
2. Discussion of the Related Art
In a memory circuit array such as DRAM, each memory cell comprises a capacitor that can be electrically isolated by a switch. The capacitor of each cell is at a high supply voltage Vdd or at a low voltage, for example zero, according to whether the memory cell stores a “1” or a “0”. To read the information stored in a memory cell, the cell capacitor is connected to a bit line connected to a memory cell column, and a sense amplifier is used to detect the bit line voltage.
FIG. 1 schematically shows a sense amplifier connected to a bit line BL likely to be connected by a switch SW to a memory cell M symbolized by a capacitor C. A single memory cell M is shown although, in practice, several memory cells are likely to be connected to bit line BL. The sense amplifier comprises an N-channel transistor T0 having its gate connected to bit line BL and having its drain connected to a reference bit line BLref having the same electric characteristics as bit line BL. An N-channel transistor T1 has its gate connected to line BLref and its drain connected to line BL. A P-channel transistor T2 has its gate connected to the drain of transistor T1, its drain connected to the drain of transistor T0, and its source connected to a supply voltage Vdd. A P-channel transistor T3 has its gate connected to the drain of transistor T0, its drain connected to the drain of transistor T1, and its source connected to voltage Vdd. The sources of transistors T0 and T1 are connected to the drain of an N-type transistor T4. The source of transistor T4 is grounded and its gate receives a signal Sense for activating the sense amplifier. Precharge blocks Pr, activable by signals not shown, are connected to lines BL and BLref.
Lines BL and BLref are conventionally precharged to a reference voltage by blocks Pr before reading of the information stored in the memory cell. The particularly simple case where the reference voltage is the high circuit supply voltage (Vdd) is here considered. Once the precharge is over, lines BL and BLref are isolated. To read the content of a cell, switch SW is turned on. If cell M stores voltage Vdd (state “1”), the voltage of line BL is not modified. However, if cell M stores the zero voltage (state “0”), line BL discharges into capacitor C to reach an equilibrium voltage Vdd-δV ranging between Vdd and 0V. A predetermined time period after the closing of switch SW, signal Sense is activated to turn on transistor T4.
If bit line BL is at voltage Vdd-δV when transistor T4 is on, transistor T0 is controlled by a voltage Vdd-δV and transistor T1 is controlled by voltage Vdd. Bit line BL then discharges to ground through transistor T1 faster than bit line BLref discharges to ground through transistor T0. The voltage of line BL decreases faster than the voltage of line BLref, which turns on transistor T2 before transistor T3. This forces lines BLref to voltage Vdd, forces transistors T1 and T3 respectively to the on and off states, and forces line BL to ground. The state of line BL can then be read by a digital means not shown, and the reading of state “0” from cell M is ended. The bit lines may again be precharged to read the information stored in another memory cell, not shown.
If bit line BL is at voltage Vdd when transistor T4 is on (the memory point stores a 1), transistors T0 and T1 are controlled by the same voltage Vdd. The dimensions of transistors T0 and T1 must be different for transistor T0 to conduct a greater current than the current flowing through transistor T1. The voltage of line BLref thus decreases faster than the voltage of line BL, which turns on transistor T3 before transistor T2. The turning-on of transistor T3 forces line BL to voltage Vdd, which provides a digital value “1” to a read means not shown, and forces transistors T0 and T2 respectively to the on and off states. The operation of reading state “1” from cell M is then over. It should be noted that if transistors T0 and T1 were identical, one or the other of lines BL or BLref would switch to ground at the end of the reading of a “1”, in undetermined fashion. The reading of a “1” could then not be surely differentiated from the reading of a “0”.
The use of the reference bit line, to which usable memory cells cannot be connected, reduces the integration density of a memory circuit comprising sense amplifiers such as in FIG. 1.
Structures with symmetrical sense amplifiers connected to two functional bit lines enabling indifferent reading from a memory cell connected to one or the other of the bit lines are known. Such amplifiers enable reading from twice as many memory cells as the amplifier of FIG. 1, but they only operate if the bit lines are precharged to an intermediary voltage (for example, Vdd/2) between supply voltage Vdd and the ground. The generation of voltage Vdd/2 poses many problems, especially consumption and stability problems.